FeRAM

MB97R8110  Overview

FeRAM MB97R8110 Embedded UHF Band RFID LSI  For Battery-less Solution

MB97R8110 FEATURES

• Compliant with EPC global Class 1 Generation 2 (C1G2)

－Carrier frequency: 860 to 960 MHz

－Data rate

R/W → Tag: 26.7 kbps to 128 kbps (assuming equiprobable data)

Tag → R/W: 40 kbps to 640 kbps

• RF Generated Power supply to external devices (3.0V 600uA output from +8dBm RF input)
• Serial Interface (SPI)

－Slave mode operation : USER memory area can be read/written through SPI.

－Master mode operation : External SPI slave device can be controlled through SPI.

－Arbitration feature between RF and SPI access controlled by SPIREQ and SPIACK.

• Key Matrix Scan Interface
• FeRAM: Non-volatile memory with High speed read and write endurance

－USER bank size: 61,440 bits

－EPC length: up to 480bits

－BlockPermalock: 8 Areas of USER bank to be write-protected in units of 512 words (=8,192bits).

－Read/Write Endurance: 10 trillion times.

－Memory data maintenance period: 10 years (+85 ºC)

*In SPI Master communication, 28,672bits of memory can be allocated for the buffer of data to be

transferred to external slave device and the storage of response data from external SPI slave device.

MB97R8110 SPI Interface

This LSI is with SPI (Serial Peripheral Interface) interface that can be operated by the following features.

・As SPI slave device, the memory data can be accessed through the SPI interface (External power is required for the operation).

・As SPI master device, the external SPI slave device can be controlled by RF command (RF generated power is supplied for the external device).

This LSI supports SPI mode 0 (CPOL=0, CPHA=0).

SPI Slave Interface

Connection to SPI Interface

When this LSI is used as SPI slave device, the connection with SPI controller (master) shall be as shown in picture SPI Slave interface connection.

In order to start SPI slave communication, external SPI master device shall set SPIREQ to “H” level to request the communication. After SPIACK outputs “H” level, XCS shall be set to “L” level. And then SPI slave communication will be enabled. SPI controller shall stay SPIREQ “H” level, and can continue to execute commands without any interruption from RF interface during when SPIACK is “H” level. Any command from RF interface is invalid during SPI slave operation. When SPIACK is “L” level, SPI slave communication cannot be enabled.

Power down mode

When SPI master operation is disabled, if SPIREQ is switched to “L” level, this LSI will be in power down mode, which enables to reduce current consumption between VDD-VSS. (refer to 8.4.1) All the input pins excepting VDD shall be “L” level during power down mode. When SPI master operation is enabled and SPIREQ is “L” level, it is prohibited to make XCS and SCK “L” level in order to avoid conflict with SPI master operation.

SPI Master Interface

Connection to SPI Interface

When this LSI is used as SPI master device, the connection with external SPI slave device shall be as shown in Figure SPI master interface connection 1 and Figure SPI master interface connection 2. It is recommended to connect capacitor between VDOUT3 and VSS, when external SPI slave device operation causes rapid current consumption. And power supply to external SPI slave device is recommended to be controlled by “H” level output from any bit out of COM[2:0] of GPIO (refer to Chapter 7.2.1). VDIO output shall be connected to VOPSPI3, and VDOUT18 output shall be connected to VOPSPI18. In this case “H” level output of COM[2:0] will be the same as the voltage level input from VOPSPI3 .

Figure SPI master interface connection 1 shows an example of SPI master interface connection, in which XRST and CD pins are used for the connection. And DI and DO are connected with external SPI slave device respectively. Busy signal of external SPI slave device is connected to INT pin, which is assigned in GPIO interface, and busy status can be read by Reader/Writer (refer to 7.2.2).

Figure SPI master interface connection 2 shows another example of SPI master interface connection, in which XRST, CD, and INT pins are not used for the connection. And DI and DO is used as common bus connection (Mux).

Usage

GPIO can be useed as the following application scenarios.

・LED ON/OFF control

・Power supply to external SPI slave device under SPI master operation

・Status monitoring of external connected devices

Details