Bluetooth IC

1. Goodix Bluetooth IC GR551x series Overview

The Goodix bluetooth IC GR551x family is a single-mode, low-power Bluetooth 5.1 System-on-Chip (SoC). It can be configured as a Broadcaster, an Observer, a Central, or a Peripheral and supports the combination of all the above roles, making it an ideal choice for Internet of Things (IoT) and smart wearable devices.

Based on ARM^® Cortex^®-M4F CPU core, the GR551x series integrates Bluetooth 5.1 Protocol Stack, a 2.4 GHz RF transceiver, on-chip programmable Flash memory, RAM, and multiple peripherals.

GR551x SoCs are available in multiple packages (see table1) that meet your diverse project demands.

2. Bluetooth IC GR551X Features

• A Bluetooth Low Energy (Bluetooth LE) 5.1 transceiver integrates Controller and Host layers
◦ Supported data rates: 1 Mbps, 2 Mbps, and Long Range (500 kbps, 125kbps)
◦ TX power: -20 dBm to +7 dBm
◦ -96 dBm sensitivity (in 1 Mbps mode)
◦ -93 dBm sensitivity (in 2 Mbps mode)
◦ -99 dBm sensitivity (in Long Range 500 kbps mode)
◦ -102 dBm sensitivity (in Long Range 125 kbps mode)
◦ TX current: 5.6 mA @ 0 dBm, 1 Mbps
◦ RX current: 4.8 mA @ 1 Mbps
• ARM®Cortex®-M4F 32-bit micro-processor with floating point support
◦ Up to 64 MHz clock frequency

◦  Built-in Memory Protection Unit (MPU) supporting eight programmable regions

◦  Hardware Floating Point Unit (FPU)

◦ Built-in Nested Vectored Interrupt Controller (NVIC)

◦ Non-maskable Interrupt (NMI) input

◦ Serial Wire Debug (SWD) with 6 breakpoints, two watchpoints, and a debug timestamp counter

◦ 51 µA/MHz execution from Flash @ 3.3 V, 64 MHz

• On-chip memory

◦ 256 KB SRAM with retention capabilities (four 8 KB SRAM blocks and seven 32 KB SRAM blocks) for GR5515 series SoCs, and 128 KB SRAM with retention capabilities (four 8 KB SRAM blocks and three 32 KB SRAM blocks) for the GR5513 SoC

◦8 KB cache SRAM with retention capabilities

◦Stack ROM (including boot ROM and Bluetooth LE Stack)

◦1 MB internal QSPI Flash for GR5515 series SoCs and 512 KB internal QSPI Flash for the GR5513 SoC(exceptions: GR5515I0NDA requiring external QSPI Flash and GR5515IENDU requiring 512 KB embeddedFlash)

• Digital peripherals

◦One general-purpose DMA engine with 8 channels and 16 handshaking interfaces

• Analog peripherals

◦One 13-bit Sense ADC with the sampling rate of 1 Msps. It supports up to five external I/O channels and three internal signal channels

◦Built-in temperature and voltage sensors

◦Low-power comparator, supporting wakeup from deep sleep mode

• Flexible serial peripherals

◦2 x QSPI interfaces, up to 32 MHz

◦2 x UART modules up to 4 Mbps, with all modules supporting flow control and only UART0 supporting DMA

◦2 x I2C modules for peripheral communication, up to 2 MHz

◦1x SPI master interface and 1 x SPI slave interface for host communication, up to 32 MHz

◦2 x I2S interfaces (1 I2S master interface + 1 I2S slave interface)

◦ISO 7816 interface

• Security

◦Complete secure computing engine:

-AES 128-bit/192-bit/256-bit symmetric encryption (ECB, CBC)

-Hash-based Message Authentication Code (HMAC-SHA256)

-Public key cryptography (PKC)

-True random number generator (TRNG)

◦Comprehensive security operation mechanism:

-Secure boot

-Encrypted firmware running directly from Flash

-eFuse for encrypted key storage

-Differentiate application data key and firmware key, supporting one data key per device/product

• I/O peripherals

◦39 I/O pins in total

-26 general-purpose I/O (GPIO) pins

-8 always-on I/O (AON IO) pins, supporting wakeup from deep sleep mode

-5 mixed signal I/O (MSIO) pins, configurable to be digital/analog signal interface

• Timer

◦Two general-purpose, 32-bit timer modules

◦A timer module composed of two programmable 32-bit or 16-bit down counters

◦An internal sleep timer that can be used to wake the device up from deep sleep mode

◦Two PWM modules with edge alignment mode and center alignment mode, each with 3 channels

◦1 x real-time counter (RTC), can be used as Calendar

◦1 x AON watchdog timer, working in both system sleep and active status

• Power management

◦On-chip DC-DC to provide RF Analog voltage and supply core LDO

◦On-chip I/O LDO to provide I/O voltage and supply external components, maximum I/O LDO drive strength:30 mA

◦Programmable thresholds for brownout detection (BoD reset and BoD interrupt)

◦Supply voltage: 2.2 V to 3.8 V. The supply voltage of GR5515I0NDA (when the external Flash of

GR5515I0NDA is supplied by high voltage) shall equal the working voltage of the external QSPI Flash

◦I/O voltage: 1.8 V to 3.3 V (Typical) (for GR5515I0NDA/GR5515IENDU/GR5513BENDU Flash using high voltage, the VIO_LDO_OUT shall be connected to VBATL in schematic circuit.)

• Low-power consumption modes

◦Deep sleep mode: 2.7 µA (Typical), with full 256 KB SRAM retention

◦Ultra deep sleep mode: 1.8 µA (Typical), no SRAM retention

◦Off mode: 0.15 uA (Typical), nothing on except VBAT, and chip in reset mode

• Packages

◦QFN56: 7 mm x 7 mm, 0.40 mm pitch

◦BGA68: 5.3 mm x 5.3 mm, 0.50 mm pitch

◦BGA55: 3.5 mm x 3.5 mm, 0.40 mm pitch

◦QFN40: 5 mm x 5 mm, 0.40 mm pitch

• Operating temperature range: -40°C to +85°C